Transistor devices make up one of the integral components of today's integrated circuits. Consequently, a reduction in the size of transistors (often called "scaling") is constantly being pursued. Prior art FIG. 1 is a fragmentary cross section diagram illustrating a conventional MOS type transistor 10. The transistor 10 consists of a conductive gate region 12 overlying a thin gate oxide 14 which overlies a substrate 16. The gate 12 and the gate oxide 14 are disposed between a drain region 18 and a source region 20 which are formed in the substrate 16 having a channel region 22 located therebetween which underlies the gate 12 and the gate oxide 14.
As the conventional transistor 10 is scaled into the sub-micron range to reduce its dimensions and thereby improve the transistor packing density on a chip, the transistor 10 begins to experience hot-carrier effects, as illustrated in prior art FIG. 2. These undesirable hot-carrier effects become more evident when the transistor 10 is scaled while maintaining the supply voltage constant or when the supply voltage is not reduced as rapidly as the structural features of the transistor.
The hot-carrier effects are due to an increase in the electrical field within the channel region 22. The increased electric field causes electrons in an inversion layer 26 to be accelerated (or "heated") to an extent that several different undesirable phenomena occur. As illustrated in prior art FIG. 2, the hot-carrier effects can include charge injection, substrate current and electron injection into the gate oxide 14. Perhaps the most crucial hot-carrier effect is the charge injection into the gate oxide 14 which damages the thin oxide and leads to a time-dependent degradation of various transistor characteristics such as the threshold voltage (V.sub.T), the linear transconductance (g.sub.m) and the saturation current (I.sub.DSAT).
One prior art solution which reduces the undesired hot-carrier effects of traditional transistor structures is the lightly doped drain (LDD) transistor 30, which is illustrated in prior art FIG. 3. The LDD transistor 30 includes the gate 12 and the gate oxide 14 formed in a conventional manner, wherein a lightly doped drain extension region 32 is formed adjacent to the drain region 18 between the drain region 18 and the channel 22. The lightly doped drain extension region 32 typically reduces the electric field near the channel region 22 by about 30-40 percent and thus the hot-carrier reliability of the transistor is greatly improved. The extension region 32 reduces the electric field by effectively dropping a portion of the drain voltage across the extension region 32.
As transistor designers continue to scale down the transistor device dimensions, the junction depths of the source and drain regions (as well as the lightly doped drain extension region) also need to be reduced (i.e., make the junctions more shallow). Junction depths must be reduced in conjunction with scaling in order to prevent short channel transistor effects such as punchthrough and threshold voltage shift. One conventional approach to reducing the junction depth is to reduce the implant energy used to form the junctions and reduce the diffusion of the junctions in the vertical direction. The source/drain extension regions, however, require ultra-shallow junctions. The shallow p-type junctions needed for the source/drain extension regions of the LDD structure using B or BF.sub.2 are especially difficult to fabricate. Boron, being a light ion suffers considerable channeling during the implant and boron diffusion is enhanced in the presence of silicon interstitials during the heat treatment step, resulting in deeper than expected junctions. Thus, fabricating shallow p-type junctions for the source/drain extension regions is a big challenge for process engineers.
The current approach to forming the p-type shallow junctions involved reducing the energy of the implant and subsequently aiming to control the ion channeling during the implant and to minimize the enhanced diffusion during the heat treatment step.
Another disadvantage associated with prior art LDD transistors 30 is that they require an additional mask step in the fabrication process. Although the lightly doped drain extension region 32 is self-aligned to the gate 12, a masking step (not shown) must take place to shield portions of the semiconductor wafer where the lightly doped drain implant is not desired.
It is an object of the present invention to overcome the difficulties facing the prior art by providing a new method for fabrication of source/drain extension regions to obtain ultra shallow p-type junctions. It is also an object of the present invention to simplify the semiconductor manufacturing process by not requiring the LDD mask and thus using one less masking step.